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FEMTOCLOCKTM CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR
ICS843SDN Features
* * * * * * * * * *
One differential 3.3V LVPECL output Crystal oscillator interface designed for 23.2MHz - 30MHz, 18pF parallel resonant crystal Output frequency range: 116MHz - 150MHz VCO range: 580MHz - 750MHz Output duty cycle range: 47% - 53% RMS phase jitter @ 120MHz, using a 24MHz crystal (12kHz - 20MHz): 0.81ps (typical) Full 3.3V supply mode 0C to 70C ambient operating temperature Industrial temperature information available upon request Available in lead-free (RoHS 6) package
General Description
The ICS843SDN is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from IDT. The ICS843SDN uses a 24MHz crystal to synthesize 120MHz. The ICS843SDN uses IDT's 3rd generation low phase noise VCO technology, and can achieve <1ps rms phase jitter performance over the 12kHz - 20MHz integration range. The ICS843SDN is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
Table 1. Frequency Table - Typical Applications
Crystal Frequency (MHz) 25 24 Output Frequency (MHz) 125 120
Block Diagram
25MHz
Pin Assignment
Phase Detector VCO /5
Q nQ VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ nc
XTAL_IN
OSC
XTAL_OUT
/25 (fixed)
ICS843SDN 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
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Table 2. Pin Descriptions
Number 1 2 3, 4 5 6, 7 8 Name VCCA VEE XTAL_OUT XTAL_IN nc nQ, Q VCC Power Power Input Unused Output Power Type Description Analog supply pin. Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Differential output pair. LVPECL interface levels. Core supply pin.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC+ 0.5V 50mA 100mA 129.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Symbol VCC VCCA IEE Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Test Conditions Minimum 3.135 VCC - 0.10 Typical 3.3 3.3 Maximum 3.465 VCC 83 Units V V mA
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Table 3B. LVPECL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Symbol VOH VOL VSWING Parameter Output High Current; NOTE 1 Output Low Current; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units A A V
NOTE 1: Outputs termination with 50 to VCC - 2V.
Table 4. Crystal Characteristics
Parameter Mode of Oscillation Frequency; NOTE 1 Equivalent Series Resistance (ESR) Shunt Capacitance NOTE 1:Input frequency is limited to a range of 23.2MHz - 30MHz due to VCO range. 23.2 Test Conditions Minimum Typical Fundamental 30 40 7 MHz Maximum Units
pF
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = 0C to 70C
Parameter fOUT tjit(O) tR / tF odc Symbol Output Frequency RMS Phase Jitter, Random; NOTE 1 Output Rise/Fall Time Output Duty Cycle 120MHz, (Integration Range: 12kHz - 20MHz) 20% to 80% 100 47 Test Conditions Minimum 116 0.81 600 53 Typical Maximum 150 Units MHz ps ps %
NOTE 1: Please refer to Phase Noise Plot.
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Typical Phase Noise at 120MHz
120MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.81ps (typical)
Noise Power
dBc Hz
Offset Frequency (Hz)
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Parameter Measurement Information
2V 2V
Noise Power Phase Noise Plot
VCC VCCA
Qx
SCOPE
Phase Noise Mask
LVPECL
nQx VEE f1 Offset Frequency f2
-1.3V 0.165V
-
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V LVPECL Output Load AC Test Circuit
RMS Phase Jitter
nQ Q
nQ
80%

Q
80% VSW I N G
20% tR tF
20%
Output Duty Cycle/Pulse Width/Period
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Output Rise/Fall Time
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Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843SDN provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS843SDN has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
X1 18pF Parallel Crystal XTAL_OUT C2 27p
XTAL_IN C1 27p
Figure 2. Crystal Input Interface
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LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VCC
VCC
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V Zo = 50 125 FOUT FIN Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT Zo = 50 84 84 FIN 125
Zo = 50
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
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Schematic Example
Figure 5A shows an example of the ICS843SDN application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For a different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Two examples of LVPECL terminations are shown in this schematic. Additional approaches are shown in the LVPECL Termination Application Note.
VCC VCCA R1 10 C4 10uF C5 0.01u VCC U1 1 2 3 4 VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ nc 8 7 6 5
VCC 3.3V R2 133 R3 133
C3 0.01u Q nQ
Zo = 50 Ohm
XTAL_OUT XTAL_IN
+
Zo = 50 Ohm
-
VCC=3.3V
R4 82.5 18pF R5 82.5
C2 27pF
25MHz
X1
C1 27pF Zo = 50 Ohm + Zo = 50 Ohm R6 50 R7 50
Optional Y-Termination
R8 50
Figure 5A. ICS843SDN Schematic Example
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Schematic Example
Figure 5B shows an example of ICS843SDN P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6 There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane.
Table 6. Footprint Table
Reference C1, C2 C3 C4, C5 R2 Size 0402 0805 0603 0603
NOTE: Table 6 lists component sizes shown in this layout example.
Figure 5B. ICS843SDN PC Board Layout Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS843SDN. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS843SDN is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 83mA = 287.60mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 287.60mW + 30mW = 317.60mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.318W * 129.5C/W = 111.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5C/W 2.5 123.5C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL 50
VCC - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V.
* * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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Reliability Information
Table 8. JA vs. Air Flow Table for a 8 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5C/W 2.5 123.5C/W
Transistor Count
The transistor count for ICS843SDN is: 2395
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP Table 9. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 10. Ordering Information
Part/Order Number 843SDNAGLF 843SDNAGLFT Marking SDNAL SDNAL Package "Lead-Free" 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an LF suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Contact Information:
www.IDT.com
Sales
800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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